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An interesting blog post:
FPGA Softcore SoC shootout



6 cores, 5 architectures, including POWER, SPARC and RISC-V.
One very small, some very fast.

Nice to see ZPUFlex getting a mention there - that was one of my previous pet projects!

I say this more like comparing apples to oranges.
Important details are masked out by the WOW speed factor
of the VHDL compiler used amd the best FPGA.
I think the first version of Micro Baze
was hand compiled for speed. Using 16 bit x 1 Xilinx block rams
as a 16 x n register file and tristate logic for the ALU.
This was 20 years ago, and the link has vanished off the web.
Compare say clock cycles for instructions, and I bet most
Risc's run at the same speed.
Ben.
PS: Found the site. You have to dig a bit for the first cpu version.
http://fpgacpu.org/index.html
Let us see today vs 20 years ago.

I think you might be looking at it from a different angle from the author - I think the intention here is "So you're working on an FPGA project and you need to embed a CPU to handle housekeeping tasks. Here are some options, with the pros and cons of each."



Well he does quote DMIPS/MHz, and yes most RISC designs will have pretty similar performance - certainly within an order of magnitude - so other factors (such as footprint and how painful the CPU is to integrate or debug) will be a tiebreaker when deciding which to use.



Looks like some good reading material there - thanks for the link.