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| Design process blog: A Bug-Free RISC-V Core (no Simulation) http://anycpu.org/forum/viewtopic.php?f=3&t=751 |
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| Author: | BigEd [ Mon Jun 22, 2020 7:12 pm ] |
| Post subject: | Design process blog: A Bug-Free RISC-V Core (no Simulation) |
. worth a read. Using formal methods and the RISC-V testsuite. Tackling a simple machine first, but with some thinking ahead, with the aim of hitting reasonable performance: https://tomverbeure.github.io/risc-v/20 ... ation.html A very different kind of debugging progress compared to the usual approach using simulation - and overall more time-efficient, I reckon. But, you do need the testsuite, which in the case of RISC-V has been written for you, and in the case of a homebrew CPU that would be a major task with its own kind of expertise. |
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| Author: | oldben [ Mon Jun 22, 2020 10:15 pm ] |
| Post subject: | Re: Design process blog: A Bug-Free RISC-V Core (no Simulati |
How ever formal logic still cannot stop simple typo or logic errors. Working a on cross compiler with two versions, I had a output print out of 130 pages with only two typo errors. 1 #define BPW 4 rather than the correct #define BPW 2 for that machine and forgotton & for &p->name[0] Ben. |
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