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I came across some teaching materials based on RISC-V, the open source architecture, which include a web-based emulation of the machine - making the CPU visible. I rather like that sort of thing, especially because everyone has a web browser and there's no barrier to just having a go. Here's the video, on YouTube:
emulsiV: A visual simulator for teaching computer architecture using the RISC-V instruction setHere's the emulator (
and here's the source)
http://tice.sea.eseo.fr/riscv/Quote:
emulsiV is a visual simulator for Virgule, a minimal CPU core implementation based on the RISC-V architecture. This simulator is intended to be used as a tool for teaching the basics of computer architecture.
The user interface shows the structure of the datapath and animates the data transfers between functional units. The execution of a single instruction is decomposed into several steps (fetch, decode, ALU, mem/reg, PC) for educational reasons, but the intent is not to reflect a specific sequencer or pipeline implementation. In fact, we don't plan to simulate a pipeline in more detail.
As it happens, the emulsiV video also mentions similar efforts which are ARM-like or ARM-based:
http://peterhigginson.co.uk/AQA/info.htmlhttps://www.peterhigginson.co.uk/ARMlite/docv1.php
