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 The Cray-1 implementation: an 80MHz machine 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
The memory subsystem I suspect made up 75% of the cost of any big machine in that era,
with big being a bus wider than 16 bits. Now days 75% of the cost a machine is the FAN and CPU, a strange contrast.
1975..1985 was the era BIG LAB computing or timesharing that is for sure.

Wed Jan 20, 2021 6:59 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
I was going to say that an FPGA's on-chip RAMs are so fast that we tend to see single-cycle access, which is very much not the territory that Cray was working in. But, it turns out that when you assemble 64k of block RAM there is a speed penalty, presumably due to routing: it's possible, perhaps, to have a well-balanced design with a very fast CPU and 2-cycle RAM, without having to slow anything down deliberately. Perhaps even more than 2 cycles.

Wed Jan 20, 2021 10:11 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2104
Location: Canada
I was thinking of trying to design a vector machine with a slightly more modern architecture. It would have 32 scalar registers, 32 vector registers. 32-bit instruction parcels rather than 16-bit.

The xc7a200t (sample FPGA) has
13Mb (200k Words) potential memory, considerably less than the Cray-1 but may still be useable.
The block ram is much faster than the 20 MHz Cray-1 memory. It could probably be made to operate without needing to be banked. But let’s bank it to be safe.
For my vector machine, I would pick a vector size then have slices of the vector processed serially. So, the control logic would be like a bit-serial machine. For instance, 32 vector registers with 64, 64-bit elements is a 4096 bits wide vector machine. Processing would be 256-bits at a time, looping sixteen times (or less depending on vector length) to process all 4096 bits.
Performance would come from processing four elements every clock cycle.

Could we start a project:’s vector machine. ANY-1 ?

I would like to implement a superscalar vector machine using mainly a brute-force approach (processing all 4096 bits at once). But alas the logic requirements are far larger than an inexpensive FPGA. Build times would be intolerable.

Robert Finch

Wed Jan 20, 2021 1:09 pm WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
A new thread for an ANY-1 is a fine idea!

(I see a whole series of Cray FAQs here.)

(And here's a High Performance Computer Architectures page on Cray 1. Interesting site, by Roland Ibbett & Nigel Topham.)

Just a little more on Cray-1 - in this Cray-XMP page there's a very brief summary with some references:

The success of the CRAY-1 within the scientific computing community can be attributed to its innovative vector architecture, dense packaging, and advanced cooling technology. The CRAY-1 design employed many state of the art architectural features such as:

    Pipelining in memory access and function units,
    Utilization of vector registers and operations chaining,
    Concurrent execution of multiple functional units,
    Interleaved memory,
    Instruction cache and lookahead,
    Massive use of parallel logic to shorten the execution time of functional units.
The vector architecture introduced, at that time, a new era in high speed computing. The well balanced [1] and compact [2] design enhanced the performance of vector as well as scalar application codes.

There are many references available that discuss in great detail the architecture, physical characteristics and usage of the CRAY-1 computer [3][4][5].

But it turns out these are conventional references, not links - although I'll add links if I find them:

Wed Jan 20, 2021 1:46 pm
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