The memory subsystem I suspect made up 75% of the cost of any big machine in that era,
with big being a bus wider than 16 bits. Now days 75% of the cost a machine is the FAN and CPU, a strange contrast.
1975..1985 was the era BIG LAB computing or timesharing that is for sure.

I was going to say that an FPGA's on-chip RAMs are so fast that we tend to see single-cycle access, which is very much not the territory that Cray was working in. But, it turns out that when you assemble 64k of block RAM there is a speed penalty, presumably due to routing: it's possible, perhaps, to have a well-balanced design with a very fast CPU and 2-cycle RAM, without having to slow anything down deliberately. Perhaps even more than 2 cycles.

I was thinking of trying to design a vector machine with a slightly more modern architecture. It would have 32 scalar registers, 32 vector registers. 32-bit instruction parcels rather than 16-bit.

The xc7a200t (sample FPGA) has
13Mb (200k Words) potential memory, considerably less than the Cray-1 but may still be useable.
The block ram is much faster than the 20 MHz Cray-1 memory. It could probably be made to operate without needing to be banked. But let’s bank it to be safe.
For my vector machine, I would pick a vector size then have slices of the vector processed serially. So, the control logic would be like a bit-serial machine. For instance, 32 vector registers with 64, 64-bit elements is a 4096 bits wide vector machine. Processing would be 256-bits at a time, looping sixteen times (or less depending on vector length) to process all 4096 bits.
Performance would come from processing four elements every clock cycle.

Could we start a project: AnyCPU.org’s vector machine. ANY-1 ?

I would like to implement a superscalar vector machine using mainly a brute-force approach (processing all 4096 bits at once). But alas the logic requirements are far larger than an inexpensive FPGA. Build times would be intolerable.

A new thread for an ANY-1 is a fine idea!

(I see a whole series of Cray FAQs here.)

(And here's a High Performance Computer Architectures page on Cray 1. Interesting site, by Roland Ibbett & Nigel Topham.)

Just a little more on Cray-1 - in this Cray-XMP page there's a very brief summary with some references:



But it turns out these are conventional references, not links - although I'll add links if I find them:

1. Srini, Vason P., and Asenjo, Jorge F., "Analysis of CRAY-lS Architecture," Proc. of the 10th Annual Internation Symp. on Computer Architecture, IEEE & ACM, 1983, pp. 194-206.

2. Hockney, R. W., and Jesshope, C. R., Parallel Computers, Adam Hilger Ltd., Bristol, 1981, pp. 69-95.

3. Johnson, Paul M., "An Introduction to Vector Processing," Computer Design, February 1978, pp. 89-97.

4. Kozdrowicki, Edward W., and Theis, Douglas J., "Second Generation of Vector Supercomputers," IEEE Computer, Vol. 14, No. 11, Nov. 1980, pp. 71-83.

5. The CRAY-1 Computer Systems, Cray Research, Inc., Pub. No. 22400088.