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 SDRAM interfacing made simple - a quest 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Ben notes that FPGA dev boards often come with SDRAM, which is not nearly so easy to use as SRAM.

oldben wrote:
One thing keeping my from buy new FPGA stuff is I don't have SDRAM module for them.
I need to write my own and SDRAM is a pain in the ass to interface, and the doc's are confusing.

What to do? Well, I don't have an answer, but I note that it's possible to treat an SDRAM as an 8x slower SRAM, and that might be enough. See this comment and links within the thread:

Here is a much simpler SDRAM implementation from the Mist/Mister project. It is the Gameboy variant that has a 64Mhz clock and accesses the ram (both reads and writes) in a fixed 8 cycles to simulate 8MHz asynchronous DRAM.

Also this comment builds on the same work:
For the retro computer version, the only components in the project are the ram test (ramtest.v), the pll (pll.v) and the very simple SDRAM controller (sdram.v). I don't think a simpler SDRAM controller than that is possible.

I have now used that simper SDRAM controller in my NES project.

But perhaps this summary is a good place to start:

Fri Jan 29, 2021 8:46 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Than You,I will keep the links in mind, as SDRAM is a Round too-It project. Ben.

Sat Jan 30, 2021 2:38 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2104
Location: Canada
The Xilinx tools allow creating a DRAM controller via a GUI that prompts for DRAM characteristics. It works. So, one does not have to roll their own controller. I suspect the other FPGA vendors are the same. The generated controller still needs to be interfaced to the system with a channel multiplexor / demultiplexor and a system cache. I found channel multiplexing (so more than one device can access the sdram) and system read caching challenging to get working at a high performance.
Its quite some fun to figure out bus bandwidth requirements and limitations for different components. Because the SDRAM is shared and audio/video use up a good chunk of the bandwidth, the cpu can be designed around bandwidth limitations. There is only so much bandwidth on a low-cost board.

Robert Finch

Sun Jan 31, 2021 4:04 am WWW
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Joined: Mon May 04, 2020 3:29 pm
Posts: 9
I've some MT48LC16M16A2 because I want make a sort of "Lab board" with a CPLD (MAX II 240 or 570), a STM32F030 MCU and a 68SEC000.
Never used SDRAM before, so I'm very curious about them....
I've all the needed parts.
The objective of this board is to have a sort of "lab" to play with a 68SEC000 and SDRAM, and having a CPLD and a MCU will enable both the way (by HW or FW) to do interesting "experiments".
The 68SEC000 can run at 3.3V, so no problem at all to this "strange" mix.

I'll start to make this board after a couple of "projects" that I've currently running...

Mon Feb 01, 2021 2:47 pm
 [ 4 posts ] 

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