Desktop calculators produced in Japan from 1968 to roughly 1971 present a unique snapshot of electronic computing technology.
This was the age of the minicomputer (PDP-8, PDP-11, DG Nova etc) and these machines represented an investment of tens of thousands of dollars.
For the office and business environment, a new market class of electronic calculating machine was required - something that would replace slower mechanical calculators, perform multi-digit, 4 function decimal arithmetic and sell for under $500.
Transistorised calculators had been around since the early 1960s, but they were expensive to build, contained hundreds of components on multiple pcbs and as such had some reliability issues.
Logic was resistor transistor logic RTL, or diode transistor logic DTL (as used in the early PDP-8) and memory was constructed from discrete transistor flip-flops.
This 1968 Canon 130S is representative of this era.
http://madrona.ca/e/eec/calcs/Canon130S.htmlFrom 1968 onwards several Japanese electronic and semiconductior companies started to produce small and medium scale integration (SSI, MSI) circuits specifically intended for the calculator market.
These included integrated bit serial adder/subtractors and multi-stage flip flops. Collectively this family of ICs has become known as JMOS (Japanese MOS).
They featured a 24V logic, where 0V represents logic 1 and -24V represents logic 0.
The flip flops were master-slave types, which had separate clocks for the master stage and for the slave stage.
http://madrona.ca/e/eec/ics/JMOS.htmlThese JMOS ICs were produced by several companies, utilised the same MOS technology, and often were produced as pin compatible alternatives from different manufacturers - a bit like the 7400 series of TTL.
To keep hardware complexity to a minimum, arithmetic was done in bit-serial fashion using not much more than a single bit full-adder and a flip flop to retain the carry status from bit to bit.
Subtraction was performed by inverting one of the operands using an XOR gate and effectively converting the carry into a borrow when required.
The Toshiba TM4006 is representative of this kind of serial adder/subtractor SSI device.
http://madrona.ca/e/eec/ics/serialadders.htmlMultiplication was performed by repeated addition of the multiplicand to an accumulator, controlled by a counter or register that held a value of the multiplier which was decremented for each addition cycle.
Division was achieved by the repeated subtraction of the divisor from the dividend, until the dividend became negative. Each successful subtraction resulted in the increment of a register containing the quotient.
Schemes were derived to improve the efficiency for both multiplication and division for multi-digit BCD operands.
One of the earlier examples of a machine using the JMOS devices is the 1970 Toshiba BC-1212. It uses 38 ICs, 54 transistors and 481 diodes.*
http://madrona.ca/e/eec/calcs/ToshibaBC1212.html* Almost all of the simple AND and OR gates were constructed from diodes, with one on each input. This accounts for the large number of diodes.
It has been reverse engineered with schematics and principle of operation fully described. The author [B Hilpert] describes it as
"At the user level this is a standard-for-the-period 4-function-with-accumulator model.
Technically, it is notable for a nice, clean, canonical state-machine design, implementing straightforward multiply and divide algorithms. Compared to many of it's period, it's easier to understand at a detailed technical level. It's a good candidate for examination into how bit-serial machines of the era work. The reverse-engineered schematic includes a state diagram and state action descriptions."
From the simple bit serial adder/subtractor such as the TM4006, the manufacturers soon began to integrate more and more of the standard BCD arithmetic logic into SSI/MSI devices - in order to reduce the chip count, and thus the assembly cost.
Hardware to calculate in BCD is significantly more complex than hardware for straight binary operations. Several of the Japanese ICs were devised to overcome these recurring BCD hardware overheads into integrated devices.
Within a few years, Texas Instruments, Rockwell, Mostek and others had designed LSI devices which would reduce the calculator chip count to perhaps 6 devices and eventually a calculator on a single chip.
The bit serial architecture lasted only a few short years, and was soon replaced with 4-bit parallel BCD arithmetic.
The Japanese calculator manufacturer Busicom approached Intel in 1969 for assistance in designing a new calculator chip set, reducing 3 LSI devices to 1 device, and this indirectly led to the development of the first commercial microprocessor - the Intel 4004.
Shift register memory was designed primarily for the bit serial calculator market, and 48-bit, 60-bit and 64-bit shift registers were created in SSI specifically to hold 12 and 15 digit BCD numbers.
Shift register memory also served the computing industry for a few years for small stores until Intel and others created commercially viable random access integrated memory.
The long 48, 60 and 64 bit shift registers, used for holding multiple BCD digits were produced in large volumes to satisfy the serial calculator market. When calculators moved to parallel arithmetic, large volumes of them appeared on the surplus market.
Don Lancaster has an interesting set of articles on using (by then, surplus) calculator shift register memory for his September 1973 TV Typewriter and other projects.
