Can a 64 bit immediate compare operation be implemented using two separate instructions as follows:
The first instruction is a compare operation that compares the upper 40 bits of the operands. The instruction sets the target register equal to the NVCZ result flags of the compare. IF the upper 40 bits of the operands are different, then the NVCZ result will be valid and the lower 24 bits don’t need to be compared and the second instruction is treated as a NOP. If the upper 40 bits of the operands are equal then the Z flag will be set in the target register during the first instruction. So if the Z flag is set in the target register of the second instruction it executes otherwise it’s a nop operation. To preserve the sign compare operation the operands of the second instruction are extended from bit 24 to 63 by the sign of the operand register.
Code:
CMPIU R5,R4,#$9876543210 ; compare upper 40 bits, set R5
CMPIL R5,R4,#$543210 ; this instruction will only be executed if R4=#$9876543210 (R5.Z=1)
The reason to approach things this way is at least two instructions are required (instructions are 16,32,48, or 64 bit) and this approach doesn’t require an intermediate register loaded with an immediate value. The instructions are still independent. Interrupts can occur between the two instructions.