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64 bit immediate compare
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 2100
Can a 64 bit immediate compare operation be implemented using two separate instructions as follows:
The first instruction is a compare operation that compares the upper 40 bits of the operands. The instruction sets the target register equal to the NVCZ result flags of the compare. IF the upper 40 bits of the operands are different, then the NVCZ result will be valid and the lower 24 bits don’t need to be compared and the second instruction is treated as a NOP. If the upper 40 bits of the operands are equal then the Z flag will be set in the target register during the first instruction. So if the Z flag is set in the target register of the second instruction it executes otherwise it’s a nop operation. To preserve the sign compare operation the operands of the second instruction are extended from bit 24 to 63 by the sign of the operand register.
Code:
CMPIU R5,R4,#\$9876543210   ; compare upper 40 bits, set R5
CMPIL R5,R4,#\$543210      ; this instruction will only be executed if R4=#\$9876543210 (R5.Z=1)

The reason to approach things this way is at least two instructions are required (instructions are 16,32,48, or 64 bit) and this approach doesn’t require an intermediate register loaded with an immediate value. The instructions are still independent. Interrupts can occur between the two instructions.

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Robert Finch http://www.finitron.ca

Tue Jul 19, 2016 3:43 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
It sounds reasonable... but is a NOP any cheaper than a CMPIL? If so, then this might be worthwhile. And, how often do you need to run a 64 bit immediate compare - does the instruction earn its keep?

Tue Jul 19, 2016 9:08 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2100
Quote:
It sounds reasonable... but is a NOP any cheaper than a CMPIL? If so, then this might be worthwhile. And, how often do you need to run a 64 bit immediate compare - does the instruction earn its keep?

The instruction might not earn it's keep, except that it makes the compiler / assembler easy to implement. It just has to echo out compare instructions for the upper and lower half rather than having to select a register and load it with an immediate value. So it's slightly higher code density too. Also it's for compares over 30 bits which is otherwise the max. I expect that some of the address comparisons in a 64 bit ISA might break the 30 bit boundary. I had thought of an instruction that includes up to about 45 bits, but I figured 64 bit support would be better.
I am still playing with the instruction set. I just wondered if reversing the order of compares could be done. This compares from highest to lowest. Usually a series of subtracts from lowest to highest would be used, then the result tested.

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Robert Finch http://www.finitron.ca

Tue Jul 19, 2016 10:48 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Ah, OK, easier toolchain is a win!

Tue Jul 19, 2016 10:57 am
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