Hi All,

Back in the 1990's Chuck Moore (Forth) and Jeff Fox were working on a new class of microprocessors that were low hardware overhead and very small instruction set.

Sadly Jeff Fox died a few years ago - but a lot of his work has been preserved on his Ultratechnology.com website.

Here's a little taster - describing Jeff and Chuck's Mup21 - a MISC Forth processor

http://www.ultratechnology.com/mup21.html


regards


Ken

It does seem to be a bit of a sweet spot, 16 or a bit more. Even our OPC5ls ended up at 17 instructions(!) and the OPC6 went on into the 20s. What we were doing was trying to minimise the complexity of the implementation. An alternative, and perhaps this is the way to look at this MISC project, is to aim to minimise the difficulty of supporting a particular application or HLL.

I recently read something about the whole RISC vs CISC, and the line it took was this: we pretty much know what a RISC looks like, it will have 5 or 6 properties out of 6 or 7 defining properties. And CISC, really, is everything else! Say that you have a RISC, and you could make a reasonable set of guesses about what it's like, whereas a CISC can look like anything.

An OISC on the other hand (that's the 4th hand now) is mostly of theoretical, esoteric, or impractical interest.

Ed,

Thanks for those links - I found Al Williams "One-Der" transport triggered architecture most interesting.

http://www.drdobbs.com/embedded-systems ... 122?pgno=1

This sheds some light on the Maxim Maxq - which is a similar architecture - and incorporated into a number of Dallas/Maxim ICs - such as their "Fuel Gauge" for battery systems and the curiously named "System Management Microcontroller" the MAX31782 - I think a multichannel fan-speed controller for server systems

http://www.mouser.com/ds/2/256/MAX31782-73273.pdf

http://pdfserv.maximintegrated.com/en/an/AN5136.pdf

There's some detail about it in this GoogleBook

https://books.google.co.uk/books?id=k9S ... xq&f=false



regards



Ken

A sort-of interesting take on the OISC idea is using a single instruction of recent x86 processors: https://www.cl.cam.ac.uk/~sd601/papers/mov.pdf.

While looking for that paper, I found this: https://github.com/jbangert/trapcc

Whilst searching for more information on Charles Moore's muP21 I came across this thesis from about 10 years ago - which looks at stack computer architecture - taking up the story from the point where Philip Koopman's book ends.

http://fpgacpu.ca/stack/Second-Generati ... ecture.pdf

These are all good finds - I won't have a chance to read until next week...

Dr. LaForest, now. has on ongoing CPU project over on github that may be of interest: Octavo. I've been following some of his work since finding the thesis linked above several years ago.

Phillip Koopman's book on stack processors is also a good read, and describes a number of Forth processor architectures. I enjoyed the PDF version of the book enough that I bought a copy from a used book dealer. For those interested in processors supporting FORTH natively, Koopman has a number of articles on the subject.

Quick quote from the thesis intro:

There's a good hint there that dynamic statistics might be quite different from static statistics, which is a useful warning, given the difference in effort needed to collect the two.