Simplfied the 32 bit cpu.
For decoding. 9 22v10's, 3 eproms, 1 74H04.
The alu,4 22v10's, 5 74ls173's, 1 74H04, 1 CYC9101 (ALU).

Why 27C64? Every other device on your list much faster. Have you considered MRAM or NVSRAM? DIP54 adaptors from chipquick. 3.3V more the challenge...

A: I have them in stock, and some flash chips @ 70 ns.
I have to stick to 28 pin DIP's, they just fit on the proto board, and I can program them.
Now I need to wait for the slow boat for china. for all the parts.
The speed will be rather slow as I have no wait states for the UARTS and RTC chips,
and I plan to a use a UART clock rate for timing.
The computer is a DOS era style design,16bit+ cpu,
Floppy,HD,1 Meg Memory, Modem,6 Mhz bus,ASCII text.
Ben.

No argue vs clearing junk box of parts already owned, but only DIP28 just fit the proto-board???

16bit (as 8+8) DIP54 same length as 2x 8bit DIP28 with one pin gap between. Allows twice the address pins. Voltage translation would be the space eater.

MRAM needs no programming ritual. Use like ordinary 35nS SRAM. But magnetic, so doesn't forget. Might return some space by replacing both RAM and ROM.

NVSRAM almost no ritual, but secret codes enable RTC and write protect blocks. External cap for shutdown. 25nS might be worth figuring how those work.

You already specify a DIP64 ALU...



https://www.everspin.com/getdatasheet/MR5A16A

Hmmm, Infineon-Cypress now lists 5V NVSRAMs.
CY14E116, CY14E256, possibly more...

Sorry about the bad photo.
As you can see, when you add real chips, (2901 40 pin dips) you don't have much room.
12 bits are a bit too small for me. I still like 18 bits but you can't cut a 2901 in half.
I might go 36 bits. 2x16 2901 + 1x4 2901. Data path wider, control logic the same.(9 bit bytes)
The proto board is for a 16 bit hex front panel.
As you can see, 15 to 21 chips max per proto board,

Correction: DIP54 is 2 holes shorter than a pair of DIP28 with a hole between.

I use 3 8 bit (e)proms no gain there. Bipolar 512x8 proms would be the correct part @ 55 ns in a 20 pin dip.
$25 each + $25 programing each.

Might look at STK11C88 5V 25nS 32Kx8 NVSRAM
Adapt from SOIC28 to DIP28 should be easy.
Shave to DIP20 might take some blue wire.
Ground excess address, relocate power and /WE.

I've a feeling 8Kx8 with RTC should also exist.
Simtek STK1743, if any can still be found.
I can't find, but also haven't searched ALI.

Search for a combo with RTC cluttered by slow
Dallas pinouts. Multiplexed address/data. Not
the kind of NVSRAM I was suggesting...

Nothing drastic as the last four SOICs I adapted.
My point of showing this: Could saw away a lot
of DIP pins without cutting into SOIC pads.
Certainly six pins from one end to make DIP22.

Or start DIP32 with SOIC28 off-center to allow
more excess to be chopped from the far end.
Bigger adaptor might end smaller, go figure...

I'll take the slow RTC anyday, plus they arrived in the mail today. This week I am wiring up the front panel then I will get back
to the i/o card.
At the moment I am torn between 8 bit and 12 bit bytes. Need to order more 40 pin dip sockets for the CY901's?, if I build a 36 bit cpu.
(3 12 bytes) per word. The 36 bit cpu has the advantage of better micocode layout,but no front panel. That saves a good bit
of logic.
Ben.

Front panel update. Power led works now, wired as noise emiting diode the first time.
Power and grounds wired up. Tomorow burn the 22v10's.

Did the 22v10's get burned?

36-bits is an interesting choice. Bound to make it more challenging for software. What toolset are you using? Are the CY901's 12-bit?

Time for the big re-think, as the CPU needs a simple mmu, and revised front panel to have system cards fit on a 98 pin AT connector slot.I may be a few pins off, so as a alternitive 2 x 54 card edge connectors will be used instead per slot.
Only after about 1978 could one have ram over 64 kb in single chasses, thus need for a mmu. 0..511 K mapped process.
512..1023K mapped bank 0. 1 meg ram max.
Ben,

I use wincupl and xgecu pro (usb programmer).
Working on the 32 bit version, then later the 36 bit version in the fall. The tool chain is a hash of
c programs for the assembler and the microcode assembler and a simpile compiled language.
Any development on the fpga card I have, tends to sloppy as a simple logic change can cause
some thing to fail, and I have start over from the last working copy, often losing a day or two work.
Most develpment now is just tweeking and revising things, with a Mother board pcb, rather than the
Protoboard I had now planned.
Ben.

I will be toying with a simple 20 bit cpu, with no MMU, and no front panel and limited byte operations and one adressing mode.
Bootstrap @ FFFFE. 128 x 16 is the prom size. I hope to program 22v10's with this data and using 22V10's put both the alu
and control logic on one PCB. If it does fit I expect run at 3 mh, two phase clock. Ben.

What? No MMU? One of my favorite MMU’s is the MC6829. It is only 1 MHz though. It can add five extra address bits to the bus, doing a 5 to 10 bit map for up to four different tasks. It could map 32 kB pages into a 32 MB memory space for a 20-bit address bus CPU.