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 clock division w/ CPLD 
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Joined: Mon Mar 05, 2018 6:28 pm
Posts: 1
I'm making a DRAM controller with an ATF1508, clocking it at 80 MHz, and was going to divide the clock in the CPLD to provide the CPU clock to a 68HC000.

Anyone know if the square wave coming out of the ATF1508 will be well-behaved, with a 50% duty cycle and reasonably sharp edges? I read reports that the 68HC000 can hit 40 MHz, so I wanted to see if I could get it up there, but I worry about whether I should just use a dedicated clock divider chip instead since the period would only be 25ns at 40 MHz

Thanks in advance,


Tue Mar 20, 2018 7:06 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1316
Welcome! I think it's difficult to say how close to 50% duty cycle you might get - the ATF1508 CPLD has a propagation delay of 7ns max, which as an indicator of how long the internal delays might be is quite a high proportion of a 12.5ns phase. You should check the datasheet of the CPU to see what duty cycle tolerance it has - it might not care too much, if internally it only uses one edge, or it could be tightly specified.

In short, I don't know, but datasheets are your friend. Really you'd like a timing analyser for your design, but I'm not aware that such things exist.

Maybe someone more knowledgeable will be able to help.

Wed Mar 21, 2018 8:44 am
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