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 A Forth CPU on FPGA for homebrew GPS 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1188
I was just reading through this fascinating but mostly over my head story of building a GPS receiver from scratch, and I see the author, Andrew Holme, uses a bespoke Forth CPU to perform some millisecond timescale tasks, freeing up FPGA fabric for the nanosecond timescale hardware engines.
http://www.aholme.co.uk/GPS/Main.htm
It's open source too, which is always nice.
http://www.aholme.co.uk/GPS/SRC/2013/Verilog/CPU.v

It's on a Spartan 3 FPGA, on a custom board:
Image

Quote:
Features:
  • FPGA resources: 360 slices + 2 BRAMs
  • Single-cycle instruction execution
  • FORTH-like, dual-stack architecture
  • 32-bit stack and ALU data paths
  • 64-bit double-precision operations
  • Hardware multiplier
  • 2k byte (expandable to 4k byte) code and data RAM
  • Macro assembler code development


Quote:
Total code plus data size of the GPS application is less than 750 words, despite all loops being unrolled.


He links also to a previous project, the TTL-based Mark 1 Forth computer:
http://www.aholme.co.uk/Mk1/Architecture.htm

Image


Wed Nov 09, 2016 9:45 am
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Joined: Tue Jan 15, 2013 5:43 am
Posts: 180
Quote:
He links also to a previous project, the TTL-based Mark 1 Forth computer

His Mark 2 is interesting, too. Among other changes, the bus width is doubled -- which slightly complicates byte addressability.


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Wed Nov 09, 2016 4:57 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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Oops - I missed that!


Wed Nov 09, 2016 4:58 pm
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