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 Tactics for small and fast FPGA implementations 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1225
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I thought it would be good to share the results of some experiments hoglet did, using the xilinx tools to implement our OPC5 core with a small code cache and an 8 bit memory controller.

The overall lesson is that both the size and speed of an implementation can vary a lot depending on the tactics used to build it, and so the quick default synthesis result should not be used to rule out any particular idea as being too large or too slow, unless it is a long way off.

Dave used SmartExplorer to run 7 tactics for place and route, in combination with either Speed or Area tactics for synthesis, in combination with two different clock speed targets. (Sometimes a mild overconstraint on timing can give better results.)

-opt_mode Speed in the .xst file 10ns timespec in .ucf file
    Minimum period: 9.538ns 104.844MHz 162 Slices
    Minimum period: 9.543ns 104.789MHz 162 Slices
    Minimum period: 9.287ns 107.677MHz 196 Slices
    Minimum period: 9.459ns 105.719MHz 163 Slices
    Minimum period: 9.535ns 104.877MHz 194 Slices
    Minimum period: 9.558ns 104.624MHz 162 Slices
    Minimum period: 9.560ns 104.603MHz 150 Slices

-opt_mode Speed in the .xst file 8ns timespec in .ucf file
    Minimum period: 8.860ns 112.867MHz 148 Slices
    Minimum period: 9.153ns 109.254MHz 158 Slices
    Minimum period: 7.508ns 133.191MHz 176 Slices
    Minimum period: 8.895ns 112.423MHz 148 Slices
    Minimum period: 8.974ns 111.433MHz 158 Slices
    Minimum period: 9.290ns 107.643MHz 158 Slices
    Minimum period: 8.467ns 118.106MHz 158 Slices

-opt_mode Area in the .xst file 10ns timespec in .ucf file
    Minimum period: 9.464ns 105.664MHz 138 Slices
    Minimum period: 9.492ns 105.352MHz 115 Slices
    Minimum period: 9.100ns 109.890MHz 174 Slices
    Minimum period: 9.412ns 106.247MHz 139 Slices
    Minimum period: 9.468ns 105.619MHz 127 Slices
    Minimum period: 9.492ns 105.352MHz 115 Slices
    Minimum period: 9.540ns 104.822MHz 130 Slices

-opt_mode Area in the .xst file 8ns timespec in .ucf file
    Minimum period: 8.280ns 120.773MHz 120 Slices
    Minimum period: 8.798ns 113.662MHz 116 Slices
    Minimum period: 7.889ns 126.759MHz 155 Slices
    Minimum period: 9.256ns 108.038MHz 121 Slices
    Minimum period: 8.835ns 113.186MHz 123 Slices
    Minimum period: 9.258ns 108.015MHz 116 Slices
    Minimum period: 9.000ns 111.111MHz 103 Slices

There are more choices possible for synthesis, and more for smartexplorer too. It's relatively easy to get smartexplorer to run 4 P&R jobs in parallel, which helps a lot on a modern multicore computer.


Fri Jul 14, 2017 4:55 am
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 918
Location: Canada
Interesting to see that the fastest times are also the largest in number of slices. Its seems to contradict the notion that small is fast.

What kind of run time was it for smart explorer ? (compared to a plain old P&R for instance).

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Robert Finch http://www.finitron.ca


Fri Jul 14, 2017 5:08 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1225
From memory, build times are a couple of minutes for each pass. So normally smartexplorer would be about 14 mins, but using 4 threads it's down below 5 mins.

I'm not too surprised that the fastest are the largest, because it allows for more redundancy - instead of one adder and some muxing, you have two dedicated adders. It's interesting that the not-quite-so-fast are sometimes a reasonable size.


Fri Jul 14, 2017 5:11 pm
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