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The ZIP cpu - a pipelined RISC
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The ZIP cpu - a pipelined RISC
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BigEd
Joined:
Wed Jan 09, 2013 6:54 pm
Posts:
1786
The ZIP cpu - a pipelined RISC
.
Just found
this blog
, with much about CPUs on FPGAs, including a CPU - the ZIP CPU.
"A small, light weight, RISC CPU soft core" with five pipeline stages.
https://github.com/ZipCPU/zipcpu
by Dan Gisselquist
Mon Sep 11, 2017 2:28 pm
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