View unanswered posts | View active topics It is currently Thu Jun 20, 2019 9:10 am

Reply to topic  [ 6 posts ] 
 Resources for Newbie Verilog and VHDL People 
Author Message

Joined: Wed May 15, 2019 1:17 am
Posts: 20
I only learned VHDL and Verilog in the past few years. As a newbie, I'd highly recommend these resources if you are starting out:

Dan is also heavily into formal verification of designs, and I'd also highly recommend that as well.

Hope you find these useful.

Mon May 20, 2019 2:23 am
User avatar

Joined: Fri Mar 22, 2019 8:03 am
Posts: 98
Location: Girona-Catalonia
Hi Warren,

Yes, that's helpful. Thanks for sharing


Mon May 20, 2019 1:37 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1190
Thanks Warren!

I've been seeking a clear and useful Verilog tutorial for some time. (I think part of the problem is that we want to use Verilog as a hardware description language, but it's designed as a hardware modelling language. I think we are best off, initially, if we just use well-tried patterns to express ourselves.)

Here are some links I've collected:

Sat May 25, 2019 4:44 pm

Joined: Tue Dec 11, 2012 8:03 am
Posts: 263
Location: California
I had a brief exposure to VHDL 20 years ago, but the project it was for got cancelled. I've never had any exposure to Verilog. How would you compare them, and under what circumstances, or for what applications, would you recommend one or the other?

_________________ lots of 6502 resources

Sun May 26, 2019 1:13 am
Profile WWW

Joined: Wed May 15, 2019 1:17 am
Posts: 20
I'm still too new to both languages to give you a good comparison between them. I like Verilog more as it's got a C-like syntax and I'm used to that. Also, there's a lot of open source support for Verilog with tools like Icarus, Verilator and yosys.

Sun May 26, 2019 2:42 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1190
Verilog is the Fortran to VHDL's Algol. Verilog is more scrappy and has obscure corners, but stick to a simple coding style and you're more productive. Verilog is a C to VHDL's Java. In VHDL there's more internal consistency checking - it's a typed language - and more verbosity. You can probably get the last bug out of a complex VHDL design more rapidly than a complex Verilog design. All my professional experience was with teams working in Verilog, mostly making CPUs and SoCs. For products in telephony and consumer electronics, you'll see Verilog used. For aerospace, maybe, you'll see VHDL.

For progress to the 99% correct, Verilog will win. For progress to 100%, VHDL will win. (This isn't true, but it might be useful!)

Sun May 26, 2019 6:59 am
Display posts from previous:  Sort by  
Reply to topic   [ 6 posts ] 

Who is online

Users browsing this forum: No registered users and 1 guest

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software