I'm working on designing a 68K computer. While reading the 16-bit READ cycle, it goes something like this:



There's more to it but you get the idea.

So, if designing an MMU with a CPLD (such as the ATF1508), I was wondering how to assert the /DTACK pin. The SRAM will take X number of ns between steps 1 and 2 of the RAM section. Once it's done (let's assume 15ns later), the CPLD needs to assert /DTACK.

But if my CPLD runs at 7.5ns, then I need a way of delaying for a bit.
If I were writing this in code, I might use something like:



My gut feeling is that since the 68K takes 8 states (cycles), that I simply wait one or two of them and assume the SRAM was ready. It would be really awesome if SRAM could work async-like and let master devices know when they are done.

Thanks for any input.

Indeed, the nature of SRAM is that you have to wait, and you get no signal or indication. So, typically, you'd use some clock and wait some number of cycles, in order to meet the datasheet timing (taking into account the delays in your glue logic of course, and maybe a little safety margin.)

The faster the clock you have to hand, the more fine-grained your counting will be. But as you note, the CPU works in discrete wait-state cycles, so it makes sense to use those to do the counting.

So, in a CPLD, you'll need one, two or three bits for a counter. I'm afraid I'm likely to get an out-by-one error, but two cycles at 7.5ns certainly does give you the 15ns which you say your SRAM will take. (I think that's pretty fast SRAM.)

If it's a 68K running at a hobbyist-friendly speed, I think you're highly unlikely to need to do much more than simply grounding /DTACK. For a read cycle, it looks like the RAM (or ROM, or I/O) has about 4 clock cycles to do what it needs to do; at 8MHz, that is 500nS.

See e.g. http://users.cecs.anu.edu.au/~Matthew.James/engn3213-2002/notes/busnode7.html

Thanks for the information.

Yeah, I was thinking of a couple of timers and just checking for the second bit or so. I haven't done the math yet, but that's the idea.

As far as speed, I plan on running between 8-10 MHz in production. For prototyping, I'm using plain-jane 55ns SRAM (2x 512KiB). But for my production run, I plan on using 16-bit SRAM running at 10ns. Mainly because I plan on driving VGA from it as well and the RAM was surprisingly cheap.

I plan on using two of these in the production run.

https://www.mouser.com/ProductDetail/87 ... 616EDBLL10

https://en.wikipedia.org/wiki/DTACK_Gro ... _the_title

Mike B.